Guide Multithreading Architecture

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If a thread forks a successor thread with control speculation, however, it must later verify all of the speculated control dependencies.

JMA: the Java-multithreading architecture for embedded processors

If any of the speculated control dependencies are false, the thread must issue a command to kill the successor thread and all of its subsequent threads. Normally the multithreaded architecture uses a thread pipelining execution model to enforce data dependencies between concurrent threads. Unlike the instruction pipelining mechanism in a superscalar processor, where instruction sequencing, data dependencies checking, and forwarding are performed by processor hardware automatically, the multithreaded architecture performs thread initiation and data forwarding through explicit thread management and communication instructions.

The execution of a thread in the multithreaded model is partitioned into several stages, each of which performs a specific function. The execution stages of a thread and the relationship between concurrent threads are shown as follows:. After a thread is initiated by its predecessor thread, it begins executing its continuation stage. The major function of this stage is to compute recurrence variables, such as loop index variables, needed to fork the next thread. The values of these variables will be forwarded to the next thread processing element before the next thread is activated.

The continuation stage of a thread ends with a fork instruction, which causes the next thread to begin. A thread may perform store operation on which later concurrent threads could be data dependent.

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These store operations are refered to as target stores TS. To reduce hardware complexity, many implementations of the multithreaded model does not allow speculation on data dependencies. To facilitate run-time data dependence checking, the addresses of these target stores need to be calculated as early as possible. The target-store-address-generation TSAG stage performs the address computation for these target stores. These addresses are stored in the memory buffer of each thread processing element and are forwarded to the memory buffers of all succeeding concurrent threads.

After a thread completes the TSAG stage and all of the target store addresses have been forwarded, it sends a tsag-done flag to the successor thread. This flag informs the next thread that it can start the computation that may be dependent on the predecessor threads. To increase the overlap between threads, the target-store-addresses-generation stage can be further partitioned into two parts. The first part is for target store addresses generations that do not have any data dependencies on earlier threads, computed quickly and forwarded to the next thread.

The second part computes unsafe target store addresses that may be data dependent on an earlier thread. The computation stage performs the main computation of a thread.

Multithreading Architecture

If the address of a load operation matches that of a target store entry in its memory buffer during this stage, the thread will either read the data from the entry if it is available or it will wait until the data is forwarded from an earlier concurrent thread. On the other hand, if the value of a target store is computed during this stage, the thread needs to forward the address and the data to the memory buffers of all its concurrent successor threads. The computation stage of a thread ends with a stop instruction.

If the control dependencies are cleared after the computation stage, the thread completes its execution by writing all of the data from the store operation in its memory buffer to memory, including data from both target and regular stores. Data from store operations need to be kept in the memory buffer until this write-back stage to prevent the memory state from being altered by a speculative thread that is subsequently aborted by an earlier concurrent thread due to an incorrect control speculation.

To maintain the correct memory state, concurrent threads must perform their write-back stages in their original order. Because all of the stores are committed thread-by-thread, write-after-read and write-after-write hazards cannot occur during run-time. Now let's see an example to show how programs are compiled and executed on a multithreaded processor. The code segment shown in follows is one of the most time-consuming loops in the normal program:.

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  • This is a while loop with exit conditions in the loop head as well as the loop body. There is a potential read-after-write data dependence across loop iterations caused by the variable minclk. This loop is very difficult to parallelize by using conventional software pipelining techniques because of its control-flow intensive loop body and the conditional loop-carried data dependence.

    However, with the help of architectural support for multiple threads of control, control speculation, and run-time dependence checking, this loop can be easily parallelized and executed on a multithreaded architecture.

    Multithreaded Architectures and Systems

    Following is the multithreaded code specially compiled for the loop. In this code, each thread corresponds to a loop iteration. The execution of each loop iteration is transformed into three explicit thread pipelining stages and an implicit write-back stage. In the continuation stage, each thread increments the recurrence variable i and forwards its new value to the next thread processing element.

    The continuation stage ends with a fork instruction to initiate the successor thread. In each thread, there is only one target store corresponding to the update of the variable minclk. The address of the variable minclk is forwarded to the next thread in the TSAG stage. Since the TSAG is not dependent on predecessor threads, it can proceed immediately after the continuation stage. In the computation stage, a thread first begins by checking if the first exit condition is true. If it is, the thread will abort its successor threads and then jump out of the loop.

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    Otherwise, the thread will perform the computation of the loop body. If both exit conditions are false, the thread will execute a stop instruction, and then automatically perform the write-back. To fully utilize the hardware support for thread-level speculative execution and run-time data dependence checking, the multithreaded architecture relies on the compiler to extract thread-level parallelism and to generate multithreaded code. Given a sequential program, the compiler first partitions the execution of the program into threads for concurrent execution. The compiler then performs thread pipelining to facilitate run-time data dependence checking.

    Both tasks require powerful program analysis and transformation techniques. Many of these techniques have been previously developed for traditional parallelizing compilers.

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    Compilers for multithreaded architecture leverages many of these techniques. In addition to generating multithreaded code, the compiler can further enhance parallelism between threads and reduce run-time data dependence checking overhead by applying some program transformation unique to the multithreaded processor. Such techniques include conversion of data speculation to control speculation, distributed heap memory management, using critical sections for order-independent operations and memory buffering in the main memory. So the multithreaded architecture is a compilation technique requirement-intensive architecture, which need advanced compilers to support its achievement of high parallelism.

    To test and evaluate the performance of multithreaded architecture, we can run original benchmark programs on the single-threaded superscalar processor models and run the transformed multithreaded programs on the multiple threaded models. We can see that the multithreaded model can further improve the performance of a single threaded superscalar architectural model for many programs, especially for those with high thread-level parallelism with little intensive loop-carried data dependencies.

    roteptentpers.tk So we can benefit from this architecture in many application fields. Exploiting more parallelism from programs is the key to improve the performance of future microprocessors. While the developed instruction-level parallelism available in a basic block or a small set of basic blocks is very limited, there is far more loop-level parallelism available in most programs.

    Difference between Multiprocessing and Multithreading

    The concurrent multithreaded architecture models, which can exploit loop-level parallelism efficiently, have a great potential to be used in future microprocessor designs. In addition, another very important application of multithreaded architecture is that the advent of hardware support for multithreading in microprocessor can also alleviate both the latency and hardware complexity of event handling.

    When the hardware detects an event in a traditional single-threaded processor, an expensive sequence of actions must take place even before any of the event handling code is executed. Consider the diagram below for a better understanding of how above program works:. Consider the python program given below in which we print thread name and corresponding process for each task:. As it is clear from the output, the process ID remains same for all threads. We use threading. In normal conditions, the main thread is the thread from which the Python interpreter was started.

    So, this was a brief introduction to multithreading in Python. The next article in this series covers synchronization between multiple threads. Multithreading in Python Set 2 Synchronization. This article is contributed by Nikhil Kumar. If you like GeeksforGeeks and would like to contribute, you can also write an article using contribute. See your article appearing on the GeeksforGeeks main page and help other Geeks. Please write comments if you find anything incorrect, or you want to share more information about the topic discussed above.

    Writing code in comment? Please use ide. Let us first understand the concept of thread in computer architecture.